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n1809hkim 20091006-s00001 no.a1578-1/18 LC75841PE overview the LC75841PE is static drive or 1/2-duty drive, microcontroller-controlled general-purpose lcd driver that can be used in applications such as frequency display in products with electronic tuning. in addition to being capable to drive up to 54 segments directly, it can control up to 4 general-purpose output ports. features ? serial data control of switching between static drive mode and 1/2 duty drive mode. when 1/1-duty: capable of driving up to 27 segments when 1/2-duty: capable of driving up to 54 segments ? serial data input supports ccb format communication with the system controller. ? serial data control of the power-saving mode based backup function and the all segments forced off function. ? serial data control of switching between the segment output port and general-purpose output port functions (up to 4 general-purpose output ports). ? serial data control of the frame frequency of the common and segment output waveforms. ? either rc oscillator operating or external clock operatin g mode can be selected with the serial control data. ? high generality, since display data is displayed directly without the intervention of a decoder circuit. ? the inh pin allows the display to be forced to the off state. ? allows compatible operation with the lc75842 (842 mode transfer function). ordering number : ena1578 cmos ic static drive, 1/2-duty drive general-purpose lcd display driver specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. ? ccb is a registered trademark of sanyo semiconductor co., ltd. ? ccb is sanyo semiconductor's original bus format. all bus addresses are managed by sanyo semiconductor for this format.
LC75841PE no.a1578-2/18 specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd -0.3 to +7.0 v v in 1 ce, cl, di, inh -0.3 to +7.0 input voltage v in 2 osc -0.3 to v dd +0.3 v output voltage v out s1 to s27, com1, com2, p1 to p4, osc -0.3 to v dd +0.3 v i out 1 s1 to s27 300 a i out 2 com1, com2 3 output current i out 3 p1 to p4 5 ma allowable power dissipation pd max ta=105 c 50 mw operating temperature topr -40 to +105 c storage temperature tstg -55 to +125 c allowable operating ranges at ta = -40 to +105 c, v ss = 0v ratings parameter symbol conditions min typ max unit supply voltage v dd v dd 4.0 6.0 v v ih 1 ce, cl, di, inh 0.45v dd 6.0 input high-level voltage v ih 2 osc external clock operating mode 0.45v dd v dd v v il 1 ce, cl, di, inh 0 0.2v dd input low-level voltage v il 2 osc external clock operating mode 0 0.2v dd v recommended external resistor for rc oscillation rosc osc rc oscillator operating mode 39 k recommended external capacitor for rc oscillation cosc osc rc oscillator operating mode 1000 pf guaranteed range of rc oscillation fosc osc rc oscillator operating mode 19 38 76 khz external clock operating frequency f ck osc external clock operating mode [figure 3] 19 38 76 khz external clock duty cycle d ck osc external clock operating mode [figure 3] 30 50 70 % data setup time tds cl, di [figure 1][figure 2] 160 ns data hold time tdh cl, di [figure 1][figure 2] 160 ns ce wait time tcp ce, cl [figure 1][figure 2] 160 ns ce setup time tcs ce, cl [figure 1][figure 2] 160 ns ce hold time tch ce, cl [figure 1][figure 2] 160 ns high-level clock pulse width t h cl [figure 1][figure 2] 160 ns low-level clock pulse width t l cl [figure 1][figure 2] 160 ns rise time tr ce, cl, di [figure 1][figure 2] 160 ns fall time tf ce, cl, di [figure 1][figure 2] 160 ns inh switching time tc inh , ce [figure 4][figure 5][figure 6] 10 s
LC75841PE no.a1578-3/18 electrical characteristics for the allowable operating ranges ratings parameter symbol pin conditions min typ max unit hysteresis v h ce, cl, di, inh 0.03v dd v i ih 1 ce, cl, di, inh v i =6.0v 5.0 input high-level current i ih 2 osc v i =v dd external clock operating mode 5.0 a i il 1 ce, cl, di, inh v i =0v -5.0 input low-level current i il 2 osc v i =0v external clock operating mode -5.0 a v oh 1 s1 to s27 i o =-20 a v dd -0.9 v oh 2 com1, com2 i o =-100 a v dd -0.9 output high-level voltage v oh 3 p1 to p4 i o =-1ma v dd -0.9 v v ol 1 s1 to s27 i o =20 a 0.9 v ol 2 com1, com2 i o =100 a 0.9 output low-level voltage v ol 3 p1 to p4 i o =1ma 0.9 v output middle-level voltage v mid com1, com2 1/2 bias i o = 100 a 1/2v dd -0.9 1/2v dd +0.9 v oscillator frequency fosc osc rc oscillator operating mode, rosc=39k , cosc=1000pf 30.4 38 45.6 khz i dd 1 v dd power-saving mode 15 i dd 2 v dd v dd =6.0v, output open, rc oscillator operating mode, fosc=38khz, static 350 700 i dd 3 v dd v dd =6.0v, output open, rc oscillator operating mode, fosc=38khz, 1/2 duty 1500 3000 i dd 4 v dd v dd =6.0v, output open, external clock operating mode, f ck =38khz, v ih 2=0.5v dd , v il 2=0.1v dd , static 450 900 current drain i dd 5 v dd v dd =6.0v, output open, external clock operating mode, f ck =38khz, v ih 2=0.5v dd , v il 2=0.1v dd , 1/2 duty 1600 3200 a
LC75841PE no.a1578-4/18 1. when cl is stopped at the low level [figure 1] 2. when cl is stopped at the high level [figure 2] 3. osc pin clock timing in external clock operating mode [figure 3] tds v il 1 v il 1 v il 1 v ih 1 v ih 1 50% v ih 1 tch tcs tcp tdh tr tf t tds v il 1 v il 1 v il 1 v ih 1 50% v ih 1 v ih 1 tch tcs tcp tdh tr tf t osc t ck l t ck h f ck = 1 t ck h+ t ck l [khz] d ck = t ck h t ck h+ t ck l 100[%] v il 2 50% v ih 2
LC75841PE no.a1578-5/18 package dimensions unit:mm (typ) 3162c pin assignment 0.1 1.7max 0.3 0.65 (0.9) (1.5) sanyo : qfp36(7x7) 19 10 18 19 27 28 36 9.0 0.5 7.0 9.0 7.0 0.15 LC75841PE top view 3 2 5 4 7 6 9 8 1 osc v dd inh v ss ce cl di com2 com1 s25 s26 s23 s24 s21 s22 s19 s20 s27 s10 s18 s17 s16 s15 s14 s13 s12 s11 19 20 22 21 24 23 27 26 25 18 17 16 15 14 13 12 11 10 s9 s8 s6 s7 p4/s4 s5 p1/s1 p2/s2 p3/s3 36 28 29 30 31 32 33 34 35
LC75841PE no.a1578-6/18 block diagram pin functions symbol pin no. function active i/o handling when unused s1/p1 to s4/p4 s5 to s27 1 to 4 5 to 27 segment outputs for displaying the display dat a transferred by serial data input. the s1/p1 to s4/p4 pins can be used as general-purpose output ports when so set up by the control data. - o open com1 com2 36 35 common driver outputs. the fr ame frequency is fo [hz]. - o open osc 28 oscillator connection. an oscillator circ uit is formed by connecting an external resistor and capacitor to this pin. this pi n can be used as the external clock input pin if external clock operating mode is selected with the control data. - i/o v dd ce cl di 32 33 34 serial data transfer inputs. must be connected to the controller. ce: chip enable cl: synchronization clock di: transfer data h - i i i gnd inh 30 display off control input ? inh = low (v ss ) ...display forced off s1/p1 to s4/p4 = low (v ss ) (these pins are forcibly set to the segment output port function and held at the v ss level.) s5 to s27 = low (v ss ) com1, com2 = low (v ss ) osc = z (high impedance) rc oscillation stopped inhibits external clock input. ? inh = high (v dd )...display on rc oscillation enabled (rc oscillator operating mode) enables external clock input (external clock operating mode) however, serial data transfer is possible when the display is forced off. l i gnd v dd 29 power supply. provide a voltage in the range 4.0 to 6.0v. - - - v ss 31 ground pin. must be connected to ground. - - - com2 s1/p1 s2/p2 s3/p3 s5 ce cl di s27 com1 v ss v dd inh osc shift register segment driver & latch ccb interface clock generator common driver s26 control register s4/p4
LC75841PE no.a1578-7/18 serial data transfer formats (1) static drive mode 1. when cl is stopped at the low level 2. when cl is stopped at the high level note: dd is the direction data. ? ccb address ....... "44h" ? d1 to d27 ......... display data ? p0 to p2 .............. segment output port/gener al-purpose output port switching control data ? dt ...................... static drive or 1/2 duty drive switching control data ? fc0 to fc2 ......... common/segment output waveform frame frequency control data ? oc ................ ...... rc oscillator operating mode/external cl ock operating mode switching control data ? sc ...................... segments on/off control data ? bu ...................... normal mode/power-saving mode control data dd 1 bit control data 12 bits display data 27 bits ccb address 8 bits b1 b0 d2 d1 0 0 d18 0 0 di cl ce 0 0 0 d21 1 0 1 b3 b2 a1 a0 a3 a2 d19 d23 d22 d24 d27 d25 oc fc2 p2 p1 0 bu sc p0 d26 dt fc0 fc1 d20 d15 d16 d17 dt oc b1 b0 d2 d1 0 0 0 0 0 d21 d16 d15 di cl ce b3 b2 a1 a0 a3 a2 1 0 1 d18 d17 d20 d19 d23 d22 d24 0 0 d27 d26 p1 p0 p2 sc 0 bu d25 fc2 fc0 fc1 dd 1 bit control data 12 bits display data 27 bits ccb address 8 bits
LC75841PE no.a1578-8/18 (2) 1/2 duty drive mode 1. when cl is stopped at the low level 2. when cl is stopped at the high level note: dd is the direction data. ? ccb address ....... "44h" ? d1 to d54 ......... display data ? p0 to p2 .............. segment output port/gener al-purpose output port switching control data ? dt ...................... static drive or 1/2 duty drive switching control data ? fc0 to fc2 ......... common/segment output waveform frame frequency control data ? oc ................ ...... rc oscillator operating mode/external cl ock operating mode switching control data ? sc ...................... segments on/off control data ? bu ...................... normal mode/power-saving mode control data dd 1 bit control data 11 bits display data 28 bits ccb address 8 bits dd 1 bit fixed data 13 bits display data 26 bits ccb address 8 bits dd 1 bit control data 11 bits display data 28 bits ccb address 8 bits dd 1 bit fixed data 13 bits display data 26 bits ccb address 8 bits b1 b0 d2 d1 0 0 d18 0 d28 di cl ce 0 0 0 d21 1 0 1 b3 b2 a1 a0 a3 a2 d19 d23 d22 d24 d27 d25 oc fc2 p2 p1 0 bu sc p0 d26 dt fc0 fc1 d20 d15 d16 d17 b1 b0 0 0 d30 d29 0 0 0 0 d52 1 0 1 b3 b2 a1 a0 a3 a2 d48 d47 d54 d53 00 01 00 0 0 0 0 0 0 0 d49 d51 d50 d45 d46 d43 d44 dt oc b1 b0 d2 d1 0 0 0 0 0 d21 d16 d15 di cl ce b3 b2 a1 a0 a3 a2 1 0 1 d18 d17 d20 d19 d23 d22 d24 0 d28 d27 d26 p1 p0 p2 sc 0 bu d25 fc2 fc0 fc1 0 b1 b0 0 0 0 0 0 d49 d44 d30 d29 b3 b2 a1 a0 a3 a2 1 0 1 d51 d50 00 01 0 d48 d47 d46 d45 0 0 0 0 0 0 0 d52 d54 d53 0 d43
LC75841PE no.a1578-9/18 serial data transfer formats (when in 842 mode data transfer) (1) 1/2 duty drive mode (when in 842 mode data transfer) 1. when cl is stopped at the low level 2. when cl is stopped at the high level note: dd is the direction data. ? ccb address ....... "44h" ? d1 to d54 ......... display data ? bu ...................... normal mode/power-saving mode control data ? sc ...................... segments on/off control data b1 b0 d2 d1 0 0 d18 bu d28 di cl ce 0 0 0 d21 1 0 1 b3 b2 a1 a0 a3 a2 d19 d23 d22 d24 d27 d25 0 0 sc d26 d20 d15 d16 d17 b1 b0 0 0 d30 d29 0 0 0 0 d52 1 0 1 b3 b2 a1 a0 a3 a2 d48 d47 d54 d53 00 0 1 0 d49 d51 d50 d45 d46 d43 d44 dd 1bit control data 3 bits display data 28 bits ccb address 8 bits dd 1bit fixed data 5 bits display data 26 bits ccb address 8 bits b1 b0 d2 d1 0 0 0 0 0 d21 d16 d15 di cl ce b3 b2 a1 a0 a3 a2 1 0 1 d18 d17 d20 d19 d23 d22 d24 bu d28 d27 d26 0 sc 0 d25 b1 b0 0 0 0 0 0 d49 d44 d30 d29 b3 b2 a1 a0 a3 a2 1 0 1 d51 d50 0 0 0 d48 d47 d46 d45 0 1 d52 d54 d53 0 d43 dd 1 bit control data 3 bits display data 28 bits ccb address 8 bits dd 1 bit fixed data 5 bits display data 26 bits ccb address 8 bits
LC75841PE no.a1578-10/18 serial data transfer examples (1) static drive mode the serial data shown in the figure below must be sent. (2) 1/2 duty drive mode ? when 29 or more segments are used 96 bits of serial data (including ccb address bits) must be sent. ? when fewer than 29 segments are used the serial data shown below (the d1 to d28 display data and the control data) must always be sent. serial data transfer examples (when in 842 mode data transfer) (1) 1/2 duty drive mode (when in 842 mode data transfer) ? when 29 or more segments are used 80 bits of serial data (including ccb address bits) must be sent. ? when fewer than 29 segments are used the serial data shown in the figure below (the d1 to d28 display data, and the control data) must be sent. 40 bits 8 bits d2 d1 d15 0 0 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d16 d17 d18 d19 d20 d21 d22 d23 d24 d26 dt d27 d28 0p0p1 p2 fc0 fc1 fc2 oc sc bu 0 0 0 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d29 d30 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 0 0 0 0 0 0 0 0 0 0 0 0 0 d25 1 40 bits 8 bits d2 d1 d15 0 0 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d16 d17 d18 d19 d21 d22 d23 d24 d26 dt d27 d28 0p0p1 p2 fc0 fc1 fc2 oc sc bu 0 d25 d20 40 bits 8 bits d2 d1 d15 0 0 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d16 d17 d18 d19 d21 d22 d23 d24 d26 dt d27 0 0 p0 p1 p2 fc0 fc1 fc2 oc sc bu 0 d25 d20 32 bits 8 bits d2 d1 d15 0 0 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d16 d17 d18 d19 d21 d22 d23 d24 d26 d27 d28 bu sc 0 0 d25 d20 32 bits 8 bits d2 d1 d15 0 0 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d16 d17 d18 d19 d20 d21 d22 d23 d24 d26 d27 d28 bu sc 0 0 0 0 1 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d29 d30 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 00000 1 d25
LC75841PE no.a1578-11/18 control data functions 1. p0 to p2: segment output port/general-purpose output port switching control data these control data bits switch the segment output port/general-purpose output port functions of the s1/p1 to s4/p4 output pins. however, segment output port is forcibly selected when in 842 mode data transfer. control data output pin state p0 p1 p2 s1/p1 s2/p2 s3/p3 s4/p4 0 0 0 s1 s2 s3 s4 0 0 1 p1 s2 s3 s4 0 1 0 p1 p2 s3 s4 0 1 1 p1 p2 p3 s4 1 0 0 p1 p2 p3 p4 note: sn (n = 1 to 4): segment output ports pn (n = 1 to 4): general-purpose output ports note that when the general-purpose output port function is selected, the correspondence between the output pins and the display data will be that shown in the table. corresponding display data output pin static drive mode 1/2 duty drive mode s1/p1 d1 d1 s2/p2 d2 d3 s3/p3 d3 d5 s4/p4 d4 d7 for example, if the general-purpose output port function is selected for the s4/p4 output pin in 1/2 duty drive mode, it will output a high level (v dd ) when display data d7 is 1, and a low level (v ss ) when d7 is 0. 2. dt: static drive mode or 1/2 duty drive mode switching control data this control data bit selects either static drive mode or 1/2 duty drive mode. however, 1/2 duty drive mode is forcibly selected when in 842 mode data transfer. dt duty drive mode output pin state (com2) 0 static drive mode v ss level 1 1/2 duty drive mode com2 note: com2?common output 3. fc0 to fc2: common/segment output waveform frame frequency control data these control data bits set the frame frequency of the common and segment output waveforms. however, fo=fosc/384 is forcibly selected when in 842 mode data transfer. control data fc0 fc1 fc2 frame frequency fo [hz] 1 1 0 fosc/768, f ck /768 1 1 1 fosc/576, f ck /576 0 0 0 fosc/384, f ck /384 0 0 1 fosc/288, f ck /288 0 1 0 fosc/192, f ck /192
LC75841PE no.a1578-12/18 4. oc: rc oscillator operating mode/external cl ock operating mode switching control data this control data bit switches the osc pin function (either rc oscillator operating mode or external clock operating mode). however rc oscillator operating mode is forcibly selected when in 842 mode data transfer. oc osc pin function 0 rc oscillator operating mode 1 external clock operating mode note: an external resistor, rosc, and an external capacitor, cosc, must be conn ected to the osc pin if rc oscillator operating mode is selected. 5. sc: segment on/off control data this control data bit controls the on/off state of the segments. sc display state 0 on 1 off note that when the segments are turned off by setting sc to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 6. bu: normal mode/power-saving mode control data this control data bit selects either normal mode or power-saving mode. bu mode 0 normal mode 1 power-saving mode. in rc oscillator operating mode (oc = 0), the osc pin o scillator is stopped, and in external clock operating mode (oc = 1), acceptance of the external clock is stopped. in this mode the common and segm ent output pins go to the v ss levels. however, s1/p1 to s4/p4 output pins that are se t to be general-purpose output ports by the control data p0 to p2 can be used as general-purpose output ports.
LC75841PE no.a1578-13/18 display data and output pin correspondence (1) static drive mode output pin com1 output pin com1 output pin com1 s1/p1 d1 s11 d11 s21 d21 s2/p2 d2 s12 d12 s22 d22 s3/p3 d3 s13 d13 s23 d23 s4/p4 d4 s14 d14 s24 d24 s5 d5 s15 d15 s25 d25 s6 d6 s16 d16 s26 d26 s7 d7 s17 d17 s27 d27 s8 d8 s18 d18 s9 d9 s19 d19 s10 d10 s20 d20 notes: this applies to the case where the s1/p1 to s4/p4 output pins are set to be segment output ports. the static drive mode cannot be select ed when in 842 mode data transfer. for example, the table below lists the output states for the s11 output pin. display data d11 output pin (s11) state 0 the lcd segment corresponding to com1 is off 1 the lcd segment corresponding to com1 is on (2) 1/2 duty drive mode output pin com1 com2 output pin com1 com2 output pin com1 com2 s1/p1 d1 d2 s11 d21 d22 s21 d41 d42 s2/p2 d3 d4 s12 d23 d24 s22 d43 d44 s3/p3 d5 d6 s13 d25 d26 s23 d45 d46 s4/p4 d7 d8 s14 d27 d28 s24 d47 d48 s5 d9 d10 s15 d29 d30 s25 d49 d50 s6 d11 d12 s16 d31 d32 s26 d51 d52 s7 d13 d14 s17 d33 d34 s27 d53 d54 s8 d15 d16 s18 d35 d36 s9 d17 d18 s19 d37 d38 s10 d19 d20 s20 d39 d40 note: this applies to the case where the s1/p1 to s4 /p4 output pins are set to be segment output ports. for example, the table below lists the output states for the s11 output pin. display data d21 d22 output pin (s11) state 0 0 the lcd segments corresponding to com1 and com2 are off. 0 1 the lcd segment corresponding to com2 is on. 1 0 the lcd segment corresponding to com1 is on. 1 1 the lcd segments corresponding to com1 and com2 are on.
LC75841PE no.a1578-14/18 output waveforms (static drive mode) output waveforms (1/2 duty, 1/2 bias drive mode) control data fc0 fc1 fc2 frame frequency fo [hz] 1 1 0 fosc/768, f ck /768 1 1 1 fosc/576, f ck /576 0 0 0 fosc/384, f ck /384 0 0 1 fosc/288, f ck /288 0 1 0 fosc/192, f ck /192 fo[hz] lcd driver output when on lcd driver output when off com1 v dd 0v v dd 0v v dd 0v lcd driver output when only lcd segments corresponding to com1 are on. com2 com1 lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when all lcd segments corresponding to com1 and com2 are on. lcd driver output when all lcd segments corresponding to com1 and com2 are off. fo[hz] 1/2v dd v dd 0v 1/2v dd v dd 0v v dd 0v v dd 0v v dd 0v v dd 0v
LC75841PE no.a1578-15/18 display control and the inh pin since the ic?s internal data (the display data d1 to d27 and the control data when in static drive mode, and the display data d1 to d54 and the control data when in 1/2 duty drive mode) is undefined when power is first applied, applications should set the inh pin low at the same time as power is applied to turn off the display (setting s1/p1 to s4/p4 and s5 to s27, com1, and com2 to the v ss level) and during this period send serial data from the controller. the controller should then set the inh pin high after the data transfer has completed. this procedure prevents unnecessary display at power on. (see figure 4, figure 5 and figure 6) ? static drive mode ? 1/2 duty drive mode ? 1/2 duty drive mode (when in 842 mode data transfer) [figure 6] v dd internal data (d1 to d28, bu, sc) internal data (d29 to d54) ce inh undefined defined undefined display data and control data transferred v il 1 tc v il 1 undefined defined undefined t1 notes: t1>0 tc ??? 10 s min [figure 5] v dd internal d1 to d28, p0 to p2, data dt, fc0 to fc2, oc, sc, bu internal data (d29 to d54) ce undefined defined undefined display data and control data transferred v il 1 tc v il 1 undefined defined undefined t1 notes: t1>0 tc ??? 10 s min inh v dd internal d1 to d27, p0 to p2, data dt, fc0 to fc2, oc, sc, bu ce [figure 4] notes: t1>0 tc ??? 10 s min v il 1 t1 display data and control data transferred tc v il 1 undefined defined undefined inh
LC75841PE no.a1578-16/18 notes on controller transf er of display data since the LC75841PE transfer the display data (d1 to d54) in two separate transfer operations in 1/2 duty drive mode, we recommend that applications make a point of completing a ll of the display data transfer within a period of less than 30ms to prevent observable degradation of display quality. osc pin peripheral circuit (1) rc oscillator operating mode (control data oc = 0) an external resistor, rosc, and an ex ternal capacitor, cosc, must be connected between the osc pin and gnd if rc oscillator operating mode is selected. (2) external clock operating mode (control data oc = 1) when the external clock operating m ode is selected, insert a current pr otection resistor rg (4.7 to 47k ) between the osc pin and external clock output pin (external oscillato r). determine the value of the resistance according to the allowable current value at the external clock output pin. also make sure that the waveform of the external clock is not heavily distorted. osc cosc rosc note: allowable current value at external clock output pin > v dd rg osc external clock output pin rg external oscillator
LC75841PE no.a1578-17/18 sample application circuit 1 static drive mode * 2: in rc oscillator operating mode, an external resistor, ro sc, and an external capacito r, cosc, must be connected between the osc pin and ground. if external clock operating mode is selected, a current protection resistor, rg (4.7 to 47k ), must be inserted between the external clock output pin (on the external oscillator) and the osc pin. (see the ?osc pin peripheral circuit? section.) * 3: when a capacitor except the recommended external capac itance (cosc = 1000pf) is co nnected to the osc pin, it should be in the range 220 to 2200pf. * 4: the pins to be connected to the controller (ce, cl, di, inh ) can handle 3.3v or 5.0v. open from the controller di cl ce inh v ss com2 s27 s26 s5 p4/s4 p2/s2 p1/s1 com1 used for functions such as backlight control general-purpose output ports (p4) (p2) (p1) osc *2 *3 +5.0v v dd lcd panel (up to 27 segments) (p3) p3/s3 *4
LC75841PE no.a1578-18/18 sample application circuit 2 1/2 duty drive mode * 2: in rc oscillator operating mode, an external resistor, ro sc, and an external capacito r, cosc, must be connected between the osc pin and ground. if external clock operating mode is selected, a current protection resistor, rg (4.7 to 47k ), must be inserted between the external clock output pin (on the external oscillator) and the osc pin. (see the ?osc pin peripheral circuit? section.) * 3: when a capacitor except the recommended external capac itance (cosc = 1000pf) is co nnected to the osc pin, it should be in the range 220 to 2200pf. * 4: the pins to be connected to the controller (ce, cl, di, inh ) can handle 3.3v or 5.0v. ps this catalog provides information as of november, 2009. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that co uld endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention cir cuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other r ights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export contro l laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any i nformation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. +5.0v v ss osc *2 *3 v dd s27 s26 s25 s5 p4/s4 p2/s2 p1/s1 com2 com1 from the controller di cl ce inh p3/s3 used for functions such as backlight control general-purpose output ports (p4) (p2) (p1) (p3) lcd panel (up to 54 segments) *4

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